发明名称 |
Data transfer control circuit with interrupt status register |
摘要 |
A data transfer control circuit includes several data receiver-transmitters, each having an interrupt identification register. Interrupt signals from the data receiver-transmitters are combined into a single interrupt signal by an interrupt controller. One of the data receiver-transmitters has an interrupt status register with bits indicating the logic levels of the interrupt signals from each of the data receiver-transmitters. A host device that receives the interrupt signal from the interrupt controller can read the interrupt status register to determine which data receiver-transmitter caused the interrupt, then read the interrupt identification register of that data receiver-transmitter to identify the interrupt source, without having to search through the interrupt identification registers of other data receiver-transmitters.
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申请公布号 |
US2002078287(A1) |
申请公布日期 |
2002.06.20 |
申请号 |
US20010975323 |
申请日期 |
2001.10.12 |
申请人 |
SHINAGAWA NORIAKI;MAEDA SHUSAKU |
发明人 |
SHINAGAWA NORIAKI;MAEDA SHUSAKU |
分类号 |
G06F13/14;G06F9/48;G06F13/12;G06F13/24;G06K19/07;(IPC1-7):G06F9/48 |
主分类号 |
G06F13/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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