| 摘要 |
A single-ended, ultra low voltage class AB power amplifier (100) including an input gain stage (102), output gain stage (104), a quiescent current control circuit (106) and a output stage bias reference circuit (108). The input gain stage (102) includes differential inputs (IN-, IN+) and differential outputs (A1, B1). The output stage (104), having control transistors, connects to each differential output (A1, B1) of the input stage (102). and a quiescent current control circuit (106) deriving common mode feedback control signal (VCS1) from the differential outputs (A1, B1) and voltage bias node (D1). A quiescent current control circuit (106) derives the common mode feedback control signal (VCS1) to maintain the voltage of the input gain stage transistors (M3, M4) at a desired level. The quiescent current control circuit (106) uses the bias voltage (VD1) supplied by an output stage bias reference (108) coupled thereto for generating the control signal (VCS1) to be applied to the gates of the input stage transistors (M3, M4), thereby maintaining the quiescent current of the output transistors (M7, M8) at a desired value.
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