| 发明名称 |
Configuration for generating a clock including a delay circuit and method thereof |
| 摘要 |
A delay locked loop (DLL) employs a gray code (an alternate code) counter as a delay register. Preventing a carry from arising at more than one bit can minimize skipping of delay time (discontinuous skipping thereof) if a metastable state should occur.
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| 申请公布号 |
US2002075047(A1) |
申请公布日期 |
2002.06.20 |
| 申请号 |
US20010877027 |
申请日期 |
2001.06.11 |
| 申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
TSUKIKAWA YASUHIKO |
| 分类号 |
G11C11/407;G06F1/10;G11C7/22;G11C8/00;H03K5/00;H03K5/14;H03K23/64;H03L7/081;H03M7/16;(IPC1-7):H03L7/06 |
主分类号 |
G11C11/407 |
| 代理机构 |
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