| 摘要 |
A circuit, which may be used in a delayed lock loop (DLL) circuit of a semiconductor memory device, for generating a timing signal includes an active circuit, a passive circuit, and a signal transition accelerating circuit. The active circuit sets a first voltage level of the timing signal in response to a clock signal. The passive circuit sets a second voltage level of the timing signal. The signal transition accelerating circuit accelerates transition of the timing signal from the first voltage level to the second voltage level, e.g., from a high level to a low level.
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