发明名称 Halbleiteranordnung mit einem auf einen Träger gelöteten Chip mit Durchgangsleitungen und Herstellungsverfahren dafür
摘要 Semiconductor device has a chip with a conductive circuit element (2) on its semiconductor substrate front face (10a), a VIA (16) extending to the conductive element (2), an earth plane (12) covering the substrate back face (10b) and the via side walls (10c) and bottom for connecting the conductive element, and a support (20) on which the chip back face (10b) is soldered. The novelty is that: (a) the chip has an anti-adhesion layer (13), deposited on the earth plane (12), only on the VIA bottom and side walls (10c) within the VIA opening, continuously down to a termination level (14c, 14c') near the substrate back face (10b); (b) the chip is fixed to the support (20) by a solder layer (14) which adheres to the earth plane (12) but which does not wet the anti-adhesion layer (13); (c) the solder layer has a planar portion (14a), between the support (20) and the substrate back face (10b), and a globular portion (14b) within the VIA opening; and (d) a free space (16a, 16b) is retained continuously around the globular solder portion between the solder and the anti-adhesion layer (13) from the VIA bottom to the termination level (40c, 40c'). Also claimed is a process for producing the above device. Preferably, the anti-adhesion layer (13) consists of conductive material, especially titanium, and the solder is a gold-tin alloy.
申请公布号 DE69712562(D1) 申请公布日期 2002.06.20
申请号 DE1997612562 申请日期 1997.02.19
申请人 KONINKLIJKE PHILIPS ELECTRONICS N.V., EINDHOVEN 发明人 BAUDET, PIERRE
分类号 H01L29/41;H01L21/338;H01L21/60;H01L21/768;H01L23/12;H01L23/48;H01L29/812;(IPC1-7):H01L21/60 主分类号 H01L29/41
代理机构 代理人
主权项
地址