发明名称 STRUCTURE OF STENCIL FOR FABRICATING STACK PACKAGE
摘要 <p>PURPOSE: A structure of a stencil for fabricating a stack package is provided to prevent a joint crack and to improve reliability of the stack package, by improving the structure of the stencil used in stacking a bottom leaded package(BLP) and a stack thin small outline package(STSOP) so that bonding force between leads is improved and an unfill defect of solder paste generated at both edges of the stack is prevented. CONSTITUTION: The stencil(3) having a line-type hole is used in applying solder paste regarding a lead positioned at both sides of the STSOP, used for stacking the BLP and the STSOP. Independent holes(40) corresponding to the number of leads at both sides of the STSOP are separated from each other by a predetermined lead pitch, formed on the stencil.</p>
申请公布号 KR20020045684(A) 申请公布日期 2002.06.20
申请号 KR20000074965 申请日期 2000.12.09
申请人 HYNIX SEMICONDUCTOR INC. 发明人 LEE, SEOK GYU
分类号 H01L21/60;(IPC1-7):H01L21/60 主分类号 H01L21/60
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