发明名称 |
Cache memory access system and method |
摘要 |
<p>A digital system is provided with a several processors, a private level one (L1) cache associated with each processor, a shared level two (L2) cache having several segments per entry, and a level three (L3) physical memory. The shared L2 cache architecture is embodied with 4-way associativity, four segments per entry and four valid and dirty bits. Multiple detection circuitry responds to several cache access requests concurrently. Multiple ports in the cache service multiple requesters concurrently if concurrent hits are determined by the detection circuitry. <IMAGE></p> |
申请公布号 |
EP1215581(A1) |
申请公布日期 |
2002.06.19 |
申请号 |
EP20000403536 |
申请日期 |
2000.12.15 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED;TEXAS INSTRUMENTS FRANCE |
发明人 |
LASSERRE, SERGE;CHAUVEL, GERARD |
分类号 |
G06F12/08;(IPC1-7):G06F12/08 |
主分类号 |
G06F12/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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