发明名称 STRUCTURE OF STENCIL FOR FABRICATING STACK PACKAGE
摘要 <p>PURPOSE: A structure of a stencil for fabricating a stack package is provided to prevent an unfill error of a solder paste generated from both edges of a stack by improving a structure of a stencil. CONSTITUTION: A stencil(3) is used for stacking a BLP(Bottom Leaded Package) and an STSOP(Stack Thin Small Outline Package). A rectangular hole(30) and an independent hole(40) are formed on a surface of a stencil(3). The rectangular hole(30) is used for applying a solder paste on a lead. The lead is located at both sides of the STSOP. The independent hole(40) has a rectangular shape. The STSOP is loaded into a groove of a jig. The STSOP is clamped by a vacuum pressure. The stencil(3) is loaded on the jig. The solder paste is applied on one side of the stencil(3). The solder paste is applied on the lead portion of the STSOP.</p>
申请公布号 KR20020044987(A) 申请公布日期 2002.06.19
申请号 KR20000074258 申请日期 2000.12.07
申请人 HYNIX SEMICONDUCTOR INC. 发明人 SONG, TAE WON
分类号 H01L21/60;(IPC1-7):H01L21/60 主分类号 H01L21/60
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