| 摘要 |
The deferred scanline converter system in accordance with the present invention receives triangle data from a front end processor, identifies the triangles that are in competition for a given pixel location, and determines the winning triangle from among the competing triangles to generate the pixel for that pixel location. The system includes a triangle buffer write logic and a scan-out logic. The triangle buffer write logic initially receives triangle data, re-orients the triangle data to top, middle, and bottom vertices, and writes the triangle data to the triangle buffer in accordance with a triangle buffer writing scheme. The writing scheme uses a coverage mask to limit the number of triangles in competition for a given pixel location (i.e., if a triangle cannot be written to the triangle buffer within the confines of the coverage mask, it will be discarded). The scan-out logic performs pixel generation so that the pixel can be generated and displayed to the monitor at the time that the pixel is generated. The scan-out logic includes a triangle cache, a column of coefficient evaluators, an array of z-interpolater processors, an image composition network, and a shading/texture mapping unit. The entire scan-out logic is pipeline for fast and efficient operation.
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