发明名称 Data channel architecture for parallel SCSI host adapters
摘要 A parallel host adapter that interfaces two I/O buses includes at least two independent data channels, a receive data channel and a send data channel. The receive data channel supports at least two data contexts. The parallel host adapter also includes an administrative information channel that couples one of the I/O buses to a memory where administrative information for the parallel host adapter is stored. The send data channel includes a send buffer memory, and a data transfer engine. The data transfer engine is coupled to a first port of the send buffer memory and to a first I/O bus coupled to the parallel host adapter. The send buffer memory is a single data context buffer memory. The receive data channel includes a receive buffer memory, and another data transfer engine. The another data transfer engine is coupled to the first I/O bus and to a first port of the receive buffer memory. Data for a first data context is transferred from the second I/O bus to the receive buffer memory through a second port of the receive buffer memory. The data in the first data context is transferred from the receive buffer memory to the first I/O bus by the another data transfer engine. As this is happening, data from a second data context can be transferred from the second I/O bus to the receive buffer memory. Also, as the receive buffer memory is emptying, the send buffer memory may be receiving data.
申请公布号 US6408354(B1) 申请公布日期 2002.06.18
申请号 US19990275652 申请日期 1999.03.24
申请人 ADAPTEC, INC. 发明人 YOUNG B. ARLEN
分类号 G06F13/28;G06F13/38;G06F13/40;(IPC1-7):G06F13/20 主分类号 G06F13/28
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