| 摘要 |
According to the present invention, a computer system and method of operation of the system is provided wherein the computer system has a memory controller which generates first and second RAS signals and Y rows of addresses in memory, and wherein the memory of the system, either as a planar or add-on memory, is configured with Y+1 rows of addresses operable by a single RAS. The system includes logic, preferably which is on an ASIC chip, to convert one of the RAS signals from the memory controller in conjunction with at least one address list to the high order address bit for the memory rows, thus constituting Y+1 rows of addressable space. The logic also generates a master RAS signal when either RAS generated by the memory controller goes active. The logic also provides for a refresh operation of all of the memory locations during a RAS only refresh operation. This is preferably controlled by a counter in the logic circuit which assures that each row gets refreshed in order when both RAS's go LOW for a refresh cycle.
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