| 摘要 |
An adder is proposed which has circuitry for calculating the sum of or difference between pairs of unpacked binary numbers having 2<n> bits or packed binary numbers having 2<n-m> bits where m < n. The adder has 2<m> sub-adders, with each sub-adder partition including a plurality of columns and a plurality of rows of cells. The columns of cells each have an input cell in the lowermost row for receiving bits of each of the pairs of numbers. Each sub-adder above the lowest significance sub-adder has a lowest significance column input cell arranged to receive a third input bit. The cells in the remaining rows of the or each sub-adder above the lowest significance sub-adder are arranged to prevent the carry-over of a carry bit from the most significant column of the preceding sub-adder being introduced into the sub-adder, depending on whether the third input bit is zero or one. |
