发明名称 Wafer metrology structure
摘要 A wafer metrology structure for measuring both critical dimension features of multiple patterns of a semiconductor device and overlay measurements of one pattern with respect to another. The measurements are readable by a single, one-dimensional scan of a metrology system. The wafer metrology structure includes at least a first feature of a first dimension formed in a first level of the semiconductor device. The first dimension is identical to a first critical dimension of a pattern formed in the corresponding first level. A wafer metrology pattern according to the present invention also includes a second pattern of a second dimension formed in a second level of the semiconductor device. The second pattern includes an aperture superposed over the first feature. The aperture exposes at least the first feature having a critical dimension of the first pattern and thus enables a metrology system to directly measure the first feature through the aperture. The second pattern also includes a feature having a second dimension identical to a second critical dimension of the second pattern formed in the corresponding second level.
申请公布号 US6407396(B1) 申请公布日期 2002.06.18
申请号 US19990339783 申请日期 1999.06.24
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 MIH REBECCA D.;SOLECKY ERIC P.;WHEELER DONALD C.
分类号 G03F7/20;H01L23/544;(IPC1-7):H01J37/304 主分类号 G03F7/20
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