| 摘要 |
A RAM (12) used by the CPU comprises a work buffer (14) and a work register (151) for pipelined processing. The work buffer (14) consists of the first to fourth work buffers (141 to 144) each of which stores information on predetermined data, e.g., a current processing on the data. When the CPU accesses the first to fourth work buffers (141 to 144), an address decoder performs an address conversion on the basis of a value (R151) of the work register (151). For example, when the value (R151) of the work register (151) is "1", addresses (P1, P2, P3 and P4) in an address space are converted (mapped) to addresses (AD141, AD142, AD143 and AD144) of work buffers (141, 142, 143 and 144). With this constitution, in performing a plurality of data processings in parallel, the CPU can improve its operation efficiency while controlling a currently performed processing on each data.
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