| 摘要 |
PROBLEM TO BE SOLVED: To provide a partial invalidation device for a cache memory which can shorten the time needed to invalidate information stored in the cache memory. SOLUTION: A select signal generating circuit 44 receives a PURGE signal 212 and a line kind signal (P-I/D)214 from a CPU 10 and attribute information from an I/D-A[i] circuit 42-i, and invalidates information stored in a V[i] circuit 48-i corresponding to the I/D-A[i] circuit 42-i by setting it to a logical value '0' when the received PURGE signal is a signal (logical value '1') indicating an invalidation request and the logical value of the received line kind signal (P-I/D)214 is equal to the logical value of the received attribute information.
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