| 摘要 |
PROBLEM TO BE SOLVED: To provide an information processing apparatus and an electronic device having an architecture capable of achieving quick response-speed without variations at the time of interrupts. SOLUTION: In the information processing apparatus to execute pipeline controls by adopting a hardware architecture, when interrupts are caused, saving processing of registers at available stages of a data buss in an instruction cycle not attended with any access to a memory is executed. At returning from the interrupts, return processing of registers at the available stages of the data buss in the instruction cycle not attended with any access to the memory in a processing routine after returning is executed. When accessing to the registers whose saving and returning have not completed yet, processing to delay the execution of access instructions to the registers is executed until the saving and returning of the registers have completed.
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