发明名称 TEST METHOD OF SEMICONDUCTOR CHIP
摘要 PROBLEM TO BE SOLVED: To reduce test time. SOLUTION: If a semiconductor chip CP1 is judged as a failure in a test process A (ST12A), the power supply 13 of the semiconductor chip CP1 is destroyed (ST16A, ST17A). Hereby, the semiconductor chip CP1 is judged as a failure in test processes B-D (step ST12B, ST12C, ST12D). Also when the semiconductor chip CP1 is judged as a failure-in test processes B-D (ST12B, ST12C, ST12D), subsequent test processes (ST13B, ST14B, ST13C, ST14C, ST13D, ST14D) for the semiconductor chip CP1 are not carried out and the test processes B-D for the semiconductor chip CP1 are terminated. Hereby, in the test processes B-D, it is possible to reduce the test time by the time (tb, tc, td) required for the subsequent test items to be tested after the failure judgment.
申请公布号 JP2002170858(A) 申请公布日期 2002.06.14
申请号 JP20000363313 申请日期 2000.11.29
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 NAKAJIMA TOSHIYUKI;HIRAYAMA TAKESHI
分类号 G01R31/28;H01L21/66;(IPC1-7):H01L21/66 主分类号 G01R31/28
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