| 摘要 |
PROBLEM TO BE SOLVED: To provide a method for fabricating a narrow wiring interval and highly integrated semiconductor device at high yield, in which a connection holes is formed surely on wiring even if there is no overlap allowance region for the connection hole. SOLUTION: A wiring 13 is covered with an insulation film 16, in which the inner region of the wiring 13 is thicker than that of the edge region. A connection hole 25 is formed by selectively etching the insulation films 24 and 16 in such a condition that the etching rate of the insulation film 16 is higher than that of the insulation film 24 on the insulation film 16. Therefore, the time until the depth of the hole 25 reaches the wiring 13 from starting of the etching of the connecting hole 25 is longer in the edge region than that of the inner region of the wiring 13 and much longer in the region shifted from the wiring 13.
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