发明名称 MANUFACTURING METHOD FOR MULTI-LAYERED WIRING BOARD
摘要 PROBLEM TO BE SOLVED: To provide a manufacturing method for a multi-layered wiring board which can form a smooth conductor layer, having a blind via hole filled with a metal conductor by a DC electrolytic method, without using a special electrolytic method or plating liquid. SOLUTION: Blind via holes 12 and 13 in closed structure are formed on one side of a resin film 10. After a conductive film 5 has been formed on the top surface of the resin film 10, including the wall surfaces of the via holes 12 and 13, a metal film 14 is formed by electroplating across the conductive film 5. For the electroplating, electroplating liquid is used having an added substance, e.g. Janus green, which is reduced and dissolved at a potential, where the metal film is deposited in the electroplating process for suppressing the deposition of the metal film and also slow in diffusion speed and has differences in the effect on the suppression of the metal film between the via hole opening upper flanks and the via hole closing lower bottom surfaces.
申请公布号 JP2002171066(A) 申请公布日期 2002.06.14
申请号 JP20000365480 申请日期 2000.11.30
申请人 HITACHI LTD 发明人 TSURUKO MASANOBU;KATSUKI MARIA;MATSUYAMA HARUHIKO
分类号 C25D7/00;H05K3/40;H05K3/46;(IPC1-7):H05K3/46 主分类号 C25D7/00
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