| 摘要 |
A FET square multiplier is disclosed that transforms an input signal into two currents I1 and I2, the difference of which is proportional to the square of the input signal. A first and a second FET are connected at their drains and are source-coupled to the source of a third FET whose transconductance is twice the transconductance of the first and the second FET. The common source node is biased by a constant current source. The FETs are operated in the saturation region to exploit the square dependency of the drain current on the difference of the gate-source voltage and the treshold voltage of an FET.
|
