| 摘要 |
<p>A semiconductor device capable of realizing a refresh test on a plurality of memories that are mounted in the same chip and can be subjected to a refresh test by using a common control signal. Any excessive refresh test can be prevented. When a first test circuit is brought into a wait state (step S2), the first test circuit issues a refresh command REF to a first memory circuit. Then, the first memory circuit refreshes memory cells until a second test circuit is brought into a wait state (step S2). Namely, the memory cells of the first memory circuit are refreshed until write of the second memory circuit ends, and therefore the refresh testing times of the first and the second memory circuits are the same.</p> |
