发明名称 Datenkommunikationssystem und Verfahren
摘要 <p>Any two multiple processor elements are coupled via a data communication network having a fixed communication buffer length and including multiple communication buffers. A packet of processed data having a header and body is created and transferred. Then a transmitting unit transmits dummy data, whose body is longer than the fixed communication buffer length, to the same receiving station. The transmitting unit then guarantees the receiving station the arrival of preceding processed data and the header. Control data representing cache invalidation waiting is embedded in the header of dummy data. When the transmitting end terminates transfer of dummy data, the sending station guarantees the termination of cache invalidation, which is performed by the receiving station to attain consistency of the contents of preceding storage data between a main storage and a cache memory. <IMAGE></p>
申请公布号 DE69331311(T2) 申请公布日期 2002.06.13
申请号 DE1993631311T 申请日期 1993.08.27
申请人 FUJITSU LTD., KAWASAKI 发明人 UENO, HARUHIKO;NAGASAWA, SHIGERU;IKEDA, MASAYUKI;SHINJO, NAOKI;ISHIZAKA, KEN-ICHI;UTSUMI, TERUO;DEWA, MASAMI;KOBAYAKAWA, KAZUSHIGE
分类号 G06F9/46;G06F12/08;G06F15/173;H04L12/70;H04L29/06;(IPC1-7):G06F9/46 主分类号 G06F9/46
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