发明名称 |
System and method of maintaining high bandwidth requirement of a data pipe from low bandwidth memories |
摘要 |
A Network Processor includes a Fat Pipe Port and a memory sub-system that provides sufficient data to satisfy the Bandwidth requirements of the Fat Pipe Port. The memory subsystem includes a plurality of DDR DRAMs controlled so that data is extracted from one DDR DRAM or simultaneously from a plurality of the DDR DRAMs. By controlling the DDR DRAMs so that the outputs provide data serially or in parallel, the data Bandwidth is adjustable over a wide range. Similarly, data is written serially into one DDR DRAM or simultaneously into multiple DDR DRAMs. As a consequence buffers with data from the same frame are written into or read from different DDR DRAMs.
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申请公布号 |
US2002071321(A1) |
申请公布日期 |
2002.06.13 |
申请号 |
US20010990840 |
申请日期 |
2001.11.21 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
BARRI PETER IRMA AUGUST;CALVIGNAC JEAN LOUIS;HASELHORST KENT HAROLD;HEDDES MARCO C.;LOGAN JOSEPH FRANKLIN;VERPLANKEN FABRICE JEAN;VRANA MIROSLAV |
分类号 |
G11C7/10;G11C11/4093;(IPC1-7):G11C7/00 |
主分类号 |
G11C7/10 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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