| 摘要 |
PURPOSE: A leakage current restraint circuit is provided to improve a cell refresh property by preventing a leakage current. CONSTITUTION: A leakage current restraint circuit comprises a plurality of memory cell array blocks(10,20,30) respectively having a cell transistor and a cell capacitor, a VBB generator(40) receiving a Vcc voltage and outputting a VBB, that is, a back bias voltage, a block selection signal generator(50) supplying one signal out of block selection signals(BS1,BS2,BS3) to the selected memory cell array block out of the memory cell array blocks(10,20,30), and a plurality of VBB transforming part(11,21,31) switching by the block selection signals(BS1,BS2,BS3) and selectively supplying the VBB voltage to the memory cell array block(10,20,30). At this circuit, when the memory cell array block(10) is selected, the other blocks(20,30) are grounded, thereby restraining a leakage current from the standby memory cell array blocks(20,30).
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