| 摘要 |
A memory access control method and system is provided for use on a computer system to control the memory access operation by a central processing unit (CPU) to a memory unit in a more efficient manner. This memory access control method and system is characterized in the capability of switching the memory access operation between a waiting mode and a non-waiting mode based on the current L1 write-back condition of the read requests from the CPU. In the waiting mode, the memory unit responds to each read request in such a manner as to wait until the L1 write-back signal of the read request is issued and then either perform a read operation for the current read request if the L1 write-back signal indicates a cache miss, or perform a cache write-back operation if the L1 write-back signal indicates a cache hit. In the non-waiting mode, the memory unit responds to each read request in such a manner that it will always promptly perform a read operation for the current read request without waiting until the CPU issues the L1 write-back signal of the current read request, and in the event that the subsequently received L1 write-back signal of the read request indicates a cache hit, promptly abandon the currently retrieved data from the memory unit and then performing a cache write-back operation.
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