| 摘要 |
A high-speed linear address generator (LAGEN) and method for generating a linear address are disclosed, which generator is operable to generate a linear address very quickly. In a preferred embodiment, the LAGEN has a parallel design, rather than a serial design, which allows the LAGEN to generate a linear address substantially faster than 1 nanosecond after receiving input operands. The LAGEN generates a linear address within a single clock cycle of a clock operating at 1 gigahertz (GHz). The LAGEN receives three 32-bit operands IMM[31:0], SRC1[31:0], and SRC2[31:0], and compresses them into two 32-bit operands. The LAGEN then sums the two operands producing a 32-bit result res[32:0]. The LAGEN allows for both 32-bit mode operation and 16-bit mode operation. In either mode of operation the lower 16 bits of the result, res[15:0], are output for the lower 16 bits of the generated linear address. The LAGEN comprises multiplexors arranged to select the output for the higher 16 bits of the linear address based upon the mode of operation for the LAGEN. Accordingly, the possible outputs for the higher 16 bits of the linear address are generated in parallel and then the appropriate one is selected for output based on the LAGEN's mode of operation.
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