发明名称 |
On-chip circuits for high speed memory testing with a slow memory tester |
摘要 |
A memory system on a semiconductor body is tested by testing components formed on the semiconductor body. A programmable clock signal generator receives an external clock signal and selectively generates an output clock signal having a frequency at a predetermined multiple of the received external clock signal. A counter receives the output clock signal from the clock signal generator and generates output signals having a cyclical binary count up to the predetermined multiple of the received external clock signal. Memory locations in a programmable look-up memory store separate commands for testing the memory system. The programmable look-up memory receives each of selective remotely generated binary encoded address signals to access a separate predetermined look-up memory section, and the binary output signals from the counter for sequentially accessing separate memory locations within the separate predetermined look-up memory section. |
申请公布号 |
US6404250(B1) |
申请公布日期 |
2002.06.11 |
申请号 |
US20010819588 |
申请日期 |
2001.03.28 |
申请人 |
INFINEON TECHNOLOGIES RICHMOND, LP |
发明人 |
VOLRATH JOERG;WHITE KEITH;EUBANKS MARK |
分类号 |
G01R31/28;G01R31/319;G11C11/401;G11C11/407;G11C29/14;G11C29/48;G11C29/50;H03L7/06;(IPC1-7):H03L7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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