| 摘要 |
Routing density estimates within a given integrated circuit are calculated from a proposed floor plan and block interconnect data. The chip is first divided into a number of grid areas, then the routing density is estimated for each grid area. This estimate is calculated by estimating grid areas that signals most likely will cross and summing probabilities. Both horizontal and vertical routing densities are estimated. The estimates for each grid area may then be saved in computer memory, printed, input to a spreadsheet, displayed on the screen, or returned in any other desired format.
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