发明名称 |
Test interface circuit and semiconductor integrated circuit device including the same |
摘要 |
In a test interface circuit arranged between an embedded memory and a test data input/output (I/O) terminal, a first-in first-out circuit for successively storing test data is arranged for controlling a latency of data read from the embedded memory. The test interface circuit for the embedded memory can reduce the number of test data I/O terminals, and can increase the executable test patterns.
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申请公布号 |
US6404684(B2) |
申请公布日期 |
2002.06.11 |
申请号 |
US20000741147 |
申请日期 |
2000.12.21 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
ARIMOTO KAZUTAMI;SHIMANO HIROKI |
分类号 |
G01R31/28;G01R31/317;G01R31/3185;G11C7/00;G11C29/00;G11C29/02;(IPC1-7):G11C7/00 |
主分类号 |
G01R31/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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