发明名称 |
Combining results of selectively executed remaining sub-instructions with that of emulated sub-instruction causing exception in VLIW processor |
摘要 |
One embodiment of the present invention provides a system that efficiently emulates sub-instructions in a very long instruction word (VLIW) processor. The system operates by receiving an exception condition during execution of a VLIW instruction within a VLIW program. This exception condition indicates that at least one sub-instruction within the VLIW instruction requires emulation in software or software assistance. In processing this exception condition, the system emulates the sub-instructions that require emulation in software and stores the results. The system also selectively executes in hardware any remaining sub-instructions in the VLIW instruction that do not require emulation in software. The system finally combines the results from the sub-instructions emulated in software with the results from the remaining sub-instructions executed in hardware, and resumes execution of the VLIW program.
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申请公布号 |
US6405300(B1) |
申请公布日期 |
2002.06.11 |
申请号 |
US19990273602 |
申请日期 |
1999.03.22 |
申请人 |
SUN MICROSYSTEMS, INC. |
发明人 |
TREMBLAY MARC;JOY WILLIAM N. |
分类号 |
G06F9/455;G06F9/30;G06F9/318;G06F9/38;(IPC1-7):G06F9/44 |
主分类号 |
G06F9/455 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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