Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric

摘要

A method of manufacturing an integrated circuit utilizes solid phase epitaxy to form an elevated source region and an elevated drain region. The method includes providing an amorphous semiconductor material and crystallizing the amorphous semiconductor material without damaging a high-k gate dielectric layer. The semiconductor material can be silicided. A shallow source drain implant can also be provide.