| 摘要 |
A method for generating a test pattern used for testing, by an LSI tester, a semiconductor integrated circuit having external terminals and sequential unitary circuits, comprising the steps of: extracting, from circuit connection information of the semiconductor, at least one sequential unitary circuit having a pair of potentially contending input terminal, and a pair of potentially contending external terminals connected to the input terminals; and further extracting therefrom a pair of actually contending external terminals connected to the same sequential unitary circuit and concurrently changing their signal level in a test pattern. On the basis of a path delay value from each of the actually contending external terminals to the corresponding sequential unitary circuit, and on the basis of the value of a tester skew, determining an optimum timing condition in the sequential unitary circuit; and generating the test pattern for the LSI tester on the basis of the optimum timing condition.
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