Integrated circuit memory devices that select sub-array blocks and input/output line pairs based on input/output bandwidth, and methods of controlling same

摘要

Integrated circuit memory devices include a memory cell block that includes sub-array blocks and a first number of input/output line pairs adjacent each of a pair of opposing sides of each of the sub-array blocks. A circuit is configured to select one of the sub-array blocks and to input/output the first number of bits of data through the first number of input/output line pairs adjacent each of the pair of opposing sides of the selected one of the sub-array blocks. The circuit is further configured to select a second number of the sub-array blocks and to input/output the first number times the second number of bits of data through the first number of input/output line pairs adjacent each of a pair of opposing sides of the selected second number of the sub-array blocks. Accordingly, the number of input/output lines need not increase even when the bandwidth increases.