发明名称 MEMORY DEVICE HAVING ADDRESS WRAP CIRCUIT
摘要 PURPOSE: A memory device having an address wrap circuit is provided to check rapidly effectiveness of a command signal and an address signal without accessing individually data of a memory device by transmitting an acknowledge signal to a memory controller. CONSTITUTION: An input buffer portion(110) receives a command signal or an address signal applied from a memory controller and transfers the received command signal or the received address signal to the inside of a memory device. An output buffer portion(150) outputs the data from the inside of the memory device to the outside. An address wrap command decoding portion(120) performs a control operation in order to transfer the command signal or the address signal applied to the input buffer portion(110) to the output buffer portion(150). A bus(130) is used for connecting a corresponding line with an output terminal of a corresponding buffer of the input buffer portion(110). A multiplexing portion(140) multiplexes the command signal or the address signal according to a control operation of the address wrap command decoding portion(120).
申请公布号 KR100341585(B1) 申请公布日期 2002.06.10
申请号 KR19980015822 申请日期 1998.05.01
申请人 HYNIX SEMICONDUCTOR INC. 发明人 CHOI, JU SEON
分类号 G11C11/408;G11C11/407;G11C29/00;G11C29/12;(IPC1-7):G11C11/407 主分类号 G11C11/408
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