| 摘要 |
The present invention relates to a method of manufacturing a flash memory cell. The present invention forms a spacer at the sidewall of a floating gate pattern to increase the surface area of the floating gate, thus increasing a dielectric film. Therefore, the present invention can increase a gate coupling ratio. Also, the present invention can reduce the distance between the floating gates to prohibit a seam phenomenon generated upon deposition of a tungsten silicide film, thus reducing a word line resistance.
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