| 摘要 |
<p>A clocked buffer amplifier circuit which is adapted to reduce the error between the input and the output by compensating for possible variations in the threshold voltage of an output transistor, the circuit including a storage capacitor which is arranged to be pre-charged to a voltage which matches the threshold voltage of the output transistor, so that the offset effect of the threshold voltage can be compensated, at the output of the amplifier.</p> |
