EMBEDDED VERTICAL DRAM CELLS AND DUAL WORKFUNCTION LOGIC GATES

摘要

A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports, comprising: Forming a french capacitor in a silicon substrate having a gate oxide layer, a polysilicon layer, and a top dialectric nitride layer deposited thereon; Applying a patterned mask over the array and support areas and forming recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Forming a silicide and oxide cap in the recesses in the nitride layer, the polysilicon layer, and shallow trench isolation region; Applying a block mask to protect the supports while stripping the nitride layer from the array and etching the exposed polysilicon layer to the top of the gate oxide layer; Striping the nitride layer from the support region and depositing a polysilicon layer over the array and support areas; Applying a mask to pattern and form a bitline diffusion stud landing pad in the array and gate conductors for the support transistors; Saliciding the tops of the landing pad and the gate conductors; Applying an interlevel oxide layer and then opening vias in the interlevel oxide layer for establishing conductive wiring channels.