发明名称 |
CORRELATION OF BEHAVIORAL HDL SIGNALS |
摘要 |
A system and method for providing correlation of HDL signal names in the structural gate level description. In one embodiment, an HDL behavioral description of a circuit is processed by a correlation compiler to identify intermediate signals. The behavioral description is modified to specify that the intermediate signals are primary outputs of the circuit. The modified behavioral description is then processed by a synthesis tool to generate a structural description corresponding to the modified behavioral description. The structural description includes as outputs the identified intermediate signals.
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申请公布号 |
WO0146874(A3) |
申请公布日期 |
2002.06.06 |
申请号 |
WO2000US34666 |
申请日期 |
2000.12.20 |
申请人 |
SPEEDGATE, INC.;SHALISH, KHALIL |
发明人 |
SHALISH, KHALIL |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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