| 摘要 |
PURPOSE: A semiconductor integrated circuit is provided to improve the accuracy of simulation analysis by reducing capacitance between wires of the real circuitry and wire dummies. CONSTITUTION: A plurality of wires(10-12) of the n-layer are arranged as circuit wires. There is no circuit wire between the wires(10,11), so that wire dummies(13) are arranged in the same n-layer in the blank area between the wires of the n-layer. The wire dummies(13) are not electrically connected to the circuit, but are provided merely for the purpose of achieving a constant wire density and constant etching conditions. In this manner, capacitance between the circuit wires of the n+1 layer and/or the n-1 layer and the wire dummies(13) of the n-layer can be reduced, thereby improving the accuracy of simulation at the time of circuit designing. Further, the parasitic capacitance of wires can be reduced in real devices, thereby reducing signal delays along the wires. |
