| 摘要 |
In a wiring condition processing method for a semiconductor integrated circuit layout information, which determines the layout of devices on the semiconductor circuit, is created based on logic information describing a connection relationship among the devices on the semiconductor. Next, a virtual wiring path is determined from the layout information. Based on the virtual wiring path, a wiring delay value is calculated. If the wiring delay value exceeds a predetermined reference value, one or more of information on the usage ratio of a wide wiring line, information on the usage ratio of a wiring layer with a small wiring load capacity, information on the usage ratio of a parallel wiring line, and information on the usage ratio of a wiring material are added to the information on the virtual wiring path to create wiring condition information.
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