发明名称 Method of fabricating reduced critical dimension for conductive line and space
摘要 A fabrication method for reducing the critical dimension of the conductive line and the space is described in which a conductive layer and a mask layer are sequentially formed on a substrate. A taper etching is conducted to form a plurality of first openings with the cross-sections of the openings being tapered off from top to bottom and exposing the surface of the conductive layer. A planarized sacrificial layer at a similar height as the mask layer is formed covering the exposed surface of the conductive layer. A second taper etching is further conducted on the exposed mask layer to form a plurality of second openings with the cross-sections of the openings being tapered off from top to bottom. The sacrificial layer is then removed. Thereafter, an anisotropic etching is conducted on the exposed conductive layer, using the mask layer as a hard mask, to form a plurality of conductive lines followed by a removal of the mask layer.
申请公布号 US6399286(B1) 申请公布日期 2002.06.04
申请号 US19990384013 申请日期 1999.08.26
申请人 TAIWAN SEMICONDUCTOR MANUFACTURING CORP. 发明人 LIU YUAN-HUNG;CHAN BOR-WEN
分类号 H01L21/3213;H01L21/768;H01L23/532;(IPC1-7):G03F7/36 主分类号 H01L21/3213
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