| 摘要 |
Disclosed is a semiconductor memory device having a master fuse circuit, and an address storage and decoding circuit. The address storage and decoding circuit stores address information to assign a defective main cell of main cells, and receives current address information in response to switch control signals. During a burn-in test mode for the main cells, the master fuse circuit generates the switch control signals in response to a bum-in test signal indicating the bum-in test, for shutting the address information off not to be provided to the address storage and decoding circuit, regardless of a connected state of the master fuse.
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