发明名称 |
MOS transistor having self-aligned well bias area |
摘要 |
A MOS transistor having a self-aligned well bias area and a method of fabricating the same provide for efficient application of well bias in a highly integrated semiconductor substrate without causing latch-up. The well bias area is formed at a trench, which is formed by etching a semiconductor substrate in a manner of self-alignment, so that well bias can be efficiently applied to the MOS transistor achieving reduction of the area of a chip without degradation of electrical characteristics.
|
申请公布号 |
US6399987(B2) |
申请公布日期 |
2002.06.04 |
申请号 |
US20010774859 |
申请日期 |
2001.01.31 |
申请人 |
SAMSUNG ELECTRONICS, CO., LTD. |
发明人 |
KIM GYU-CHUL |
分类号 |
H01L23/522;H01L21/336;H01L21/60;H01L21/74;H01L21/768;H01L21/8234;H01L21/8244;H01L27/088;H01L27/11;H01L29/78;(IPC1-7):H01L31/119 |
主分类号 |
H01L23/522 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|