| 摘要 |
PURPOSE: A test device for a semiconductor memory device is provided to detect a defective semiconductor device when a write data of a cell array is not identical with an input data of a test mode regulator, and enhances a test efficiency. CONSTITUTION: A cell array writes a data therein. A sense-amp senses a predetermined data of the cell array through a bit line. A main amplifier receives a sensing signal of the sense-amplifier through I/O line, and amplifies the sensing signal. A test mode regulator receives an output signal(INi) of the main amplifier and a control signal(TRAPA_L,TRAPA_H) being set responsive to a polarity written in the cell array, and determines whether the cell array is abnormally operated or not. As for the polarity, bits from the most significant bit to the least significant bit are all set to "HIGH" or "LOW". A data pad(DQ) receives a data stored in the cell array, and outputs an output signal from the test mode regulator.
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