| 摘要 |
PURPOSE: A clock splitter in a channel card is provided to simplify the composition of a hardware and save the embodied cost of a system by splitting various clocks of the channel card using an EPLD(Erasable Programmable Logic Device). CONSTITUTION: A TTL(Transistor-Transistor Logic) level converting unit(100) receives 2-second clocks and system clocks from a backboard(1) and converts the received 2-second clocks and system clocks into a TTL level. An EPLD(200) receives a CPU clock from a CPU(2) and simultaneously receives the second clocks and the system clocks, splits the CPU clock, the second clocks, and the system clocks into a plurality of clocks, and transmits the split clocks to a plurality of modems(3). The EPLD(200) generates a plurality of double speed system clocks and transmits the generated double speed system clocks to a plurality of modems(3).
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