发明名称 |
Memory cell configuration and method for fabricating it |
摘要 |
Layers of metallic lines and layers of memory cells are disposed alternately one above the other. The memory cells each have a diode and a memory element connected in series therewith. The memory element has a layer structure with a magnetoresistive effect. The diode has a layer structure containing at least two metal layers and an insulating layer disposed in between. The layer structure of the memory element and the layer structure of the diode are disposed above one another. The metallic lines of a respective one of the layers run parallel to one another. The metallic lines of mutually adjacent layers run transversely with respect to one another.
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申请公布号 |
US2002064069(A1) |
申请公布日期 |
2002.05.30 |
申请号 |
US20010956164 |
申请日期 |
2001.09.19 |
申请人 |
GOEBEL BERND;SCHWARZL SIEGFRIED |
发明人 |
GOEBEL BERND;SCHWARZL SIEGFRIED |
分类号 |
G11C11/14;G11C11/15;G11C11/16;H01L21/8246;H01L27/105;H01L27/22;H01L43/08;H01L49/02;(IPC1-7):G11C11/00;H01L21/82 |
主分类号 |
G11C11/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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