| 摘要 |
PROBLEM TO BE SOLVED: To provide an efficient sharing of a hardware processing stage in processing samples from a plurality of independent input sequences that are grouped prior to application to the processing arrangement by an efficient hardware architecture and processing method. SOLUTION: By applying a signal sequence Yi: j=0, 1, 2,..., MN-1} obtained by interleaving M-sets of signal sequences Xi,j: J-0, 1, 2,..., N-1; i=1, 2,..., M}, a sophisticated processing engine efficiency and/or reduction in the delay to receive the new input sample is achieved. Thus, the processing of the sample Yj is immediately started when the processing of the sample Yj-M is finished. Accordingly, a pipeline stage delay Dp can efficiently by reduced to 1/M (from Dmax to Dmax/M) and the number (or an equivalently required time) of required engines can similarly be reduced to 1/M). |
