发明名称 SEMICONDUCTOR CHIP TEST APPARATUS USING MASTER-SLAVE METHOD
摘要 PURPOSE: A semiconductor chip test apparatus using a master-slave method is provided, which improves the whole operation speed of the test apparatus by reducing the whole electrostatic capacity of a load. CONSTITUTION: A signal generator(80) receives every kinds of signals like a control signal(C), an address signal(A) and a data signal(D) and converts the received signals into a number of high output signals, and applies them to a number of slave test units(60-1,60-2,...,60-n) in common, and receives test result signals(R1,R2,...,Rn) from the slave test units. Each slave test unit includes data comparison processing unit inputting/outputting every kinds of signals to corresponding pins of a semiconductor chip and comparing/testing the data signal being output from the pin at the same position of the semiconductor chip to be tested. The test apparatus further includes buffers(90a,90b).
申请公布号 KR20020038877(A) 申请公布日期 2002.05.24
申请号 KR20000068757 申请日期 2000.11.18
申请人 MEMORY & TESTING INC. 发明人 KANG, GYEONG SEOK
分类号 H01L21/66;G01R31/3193;G11C29/00;(IPC1-7):H01L21/66 主分类号 H01L21/66
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