发明名称 SIMD ARITHMETIC SYSTEM CAPABLE OF DESIGNATING PLURAL REGISTERS
摘要 PROBLEM TO BE SOLVED: To reduce a factor for preventing SIMD operation effects, such as data arrangement in a register in the acceleration of a SIMD processor. SOLUTION: Many pieces of data can be supplied to a data arrangement operation pipe 211 and a data arrangement operation can be fast carried out by dividing a register file into four banks so as to designate a plurality of registers with one operand to simultaneously access four registers. It is also possible to efficiently arrange a large amount of data to be supplied by defining a new data pack instruction/data unpack instruction/data rearrangement instruction. It is further possible to define a product-sum operation instruction by making the best use of the parallelism of a SIMD because of the above characteristic.
申请公布号 JP2002149400(A) 申请公布日期 2002.05.24
申请号 JP20000340239 申请日期 2000.11.08
申请人 HITACHI LTD 发明人 SHIMIZU TATEHISA;ARAKAWA FUMIO
分类号 G06F7/38;G06F9/30;G06F9/302;G06F9/315;G06F9/34;G06F9/38;G06F15/80;G06F17/10;(IPC1-7):G06F9/30 主分类号 G06F7/38
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