| 摘要 |
PROBLEM TO BE SOLVED: To reduce a inter-wiring capacitance between a bit line and an upper wiring layer, in a DRAM memory cell. SOLUTION: The BPSG film 6d of a high B density is formed as an interlayer insulation film on the bit line 8, an opening part 18 is formed at the upper layer position of the bit line contact hole 7 of the BPSG film 6d, and then the opening part 18 is transformed into a void 19, whose upper part is closed by high temperature heat treatment. Thus, the void 19 of a low dielectric constant is provided on the interlayer insulation film 6d on the bit line 8, and the inter-wiring capacitance is reduced. |
